1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method and apparatus for designing a wiring pattern of the semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit apparatus which is effective for designing a semiconductor integrated circuit using a multilayer wiring layer, a wiring pattern designing method and a wiring pattern designing apparatus.
2. Description of the Related Art
In a semiconductor integrated circuit apparatus, conventionally, a multilayer wiring technique has been used to enhance a degree of integration.
If a wiring layer has the variation of wiring pattern density, there are the following two drawbacks.
As a first drawback, finishing precision in a wiring is deteriorated by a loading effect. The loading effect implies a phenomenon in which a finishing dimension of the pattern fluctuates depending on the density of the pattern. The loading effect is caused by an optical proximity effect in a photolithographic step and the excessive or insufficient amount of an etching gas in an etching step.
A second drawback relates to a controllability of an interlayer insulating film on a wiring layer.
FIG. 30 is a view showing a sectional structure of a wiring. As shown in FIG. 30, an interlayer insulating film 90 is flat in a region A in which first layer wiring patterns 10A, 10B and 10C are arranged regularly at an interval which is equal to or smaller than a predetermined interval, and a dent region is formed on the interlayer insulating film 90 so that a concavo-convex portion is generated in a region B in which the interval has a predetermined value or more as in the first layer wiring patterns 10C and 10D. A second layer wiring is formed on the concavo-convex portion. For this reason, there is a problem in that a thickness of a film is reduced in a step portion or precision in the pattern is deteriorated to cause a disconnection, and a manufacturing defective rate is increased.
Moreover, a chemical mechanical polishing method (CMP) has widely been used as a technique for flattening an interlayer insulating film. In the case in which a wiring pattern has a variation of density, however, it is hard to completely carry out the flattening. A wiring in a microfabricating process has a problem to be considered in addition to the above drawbacks.
As a third drawback, a capacitance of the wiring is changed depending on the presence of an adjacent wiring.
A wiring spacing is extremely reduced due to an increase in integration, and a parasitic capacitance between adjacent or intersecting wirings is greater than a parasitic capacitance between a signal wiring and a silicon substrate. As a result, the cross talk which causes noise and signal delay by coupling signal lines.
As a fourth drawback, a wiring resistance is increased. A thickness of a wiring is increasingly reduced due to a decrease in a wiring dimension with a process scaling and a length of the wiring is increased more and more due to a high degree of integration, and the wiring resistance is increased. For this reason, an RC delay of the wiring (a delay generated by a resistance component and a capacity component of the wiring) is greater than a transistor delay.
As the conventional art for the first and second drawbacks caused by a nonuniformity of the wiring, there has been invented an automatic wiring method for generating a flattened pattern (a wiring dummy pattern) in an empty region. For example, Patent Document 1 has disclosed an automatic wiring method for a semiconductor apparatus which serves to search for an empty region in which a wiring path is not present and to generate a redundant wiring which does not come in contact with an element and a wiring in the empty region (claim 1) in order to form a flat wiring layer without a variation in the wiring (the abstract and object of the Patent Document 1).
The automatic wiring method is executed in the following manner in accordance with a flowchart showing a flow of steps in FIG. 23.
First of all, at S100, data representing a wiring path in each layer are held in a wiring path storing apparatus.
At S200, next, an empty region in which a wiring path is not present is searched. At subsequent S300, a redundant wiring which does not come in contact with an element and a wiring is generated in the empty region.
This method will be specifically described with reference to FIG. 24. FIG. 24 shows a wiring pattern. In a semiconductor integrated circuit apparatus 700, first layer wiring patterns 10A and 10B which are vertically adjacent to each other and second layer wiring patterns 20A and 20B are shown. Moreover, description will be given on the assumption that a horizontal direction is preferentially used in the first layer wiring pattern 10 and a perpendicular direction is preferentially used in the second layer wiring pattern 20.
The first layer wiring 10 is provided on a first layer wiring grid line 11 and the second layer wiring 20 is provided on a second layer wiring grid line 21. The first layer wirings 10A and 10B and the second layer wirings 20A and 20B are connected to each other through vias 30A and 30B, 50A and 50B denote a net to be wired at an equal electric potential. FIG. 24 shows two nets 50A and 50B.
At the S100, data indicative of a wiring path in each layer based on the wiring pattern in FIG. 24 are held in a wiring path storing apparatus.
In FIG. 25, a portion related to the first layer wiring is extracted from the wiring pattern in FIG. 24. At the step S200 in which the empty region is searched, a region which is not occupied by the first layer wiring patterns 10A and 10B in the first layer wiring grid line 11 in FIG. 25 is searched as a first layer empty region 12.
At the subsequent S300, as shown in FIG. 26, redundant flattened patterns 101A, 101B and 101C which do not come in contact with the first layer wirings 10A and 10B are generated in the first layer empty region 12. In FIG. 27, the via 30 and the second layer wiring pattern 20 are added to FIG. 26.
For a conventional flattened pattern generating method, a method using a wiring pattern area ratio (a rate of an area occupied by a wiring with respect to a whole area in each wiring layer) as an index of a uniformity of the wiring has often been utilized. For example, as shown in Patent Document 2, there has been disclosed “a pattern generating method wherein a flattened pattern capable of achieving a target value of a pattern area ratio is actually disposed in an empty region of a semiconductor integrated circuit apparatus based on a result of an area ratio verifying method”. In the case in which the pattern area ratio is used, it is sufficient that the area ratio in a region to be aimed is satisfied. Therefore, a wiring may have a density locally.
In addition to the first and second drawbacks, for the drawback that the capacitance value of the wiring is changed depending on the presence of the third adjacent wiring, Patent Document 3 has disclosed a technique for disposing either an actual wiring or a dummy wiring on all grids of a semiconductor integrated circuit in order to cause a wiring capacity to be uniform, and furthermore, fixing the dummy wiring to a certain electric potential, thereby eliminating a density of the wiring and causing a capacity between the wirings to be uniform (Paragraph [0009] in the Patent Document 3).
For a fourth drawback that a wiring resistance is increased, Patent Document 4 has disclosed a semiconductor integrated circuit optimizing method for increasing a wiring width after the wiring.
FIG. 28 is a flowchart showing the conventional technique described in the Patent Document 4. An element is disposed at S50, a wiring is carded out at S60, a wiring causing a violation of a design restriction such as a delay or a cross talk is extracted at S70, a width of only a horizontal segment which is parallel with a cell row of the extracted wiring is increased at S80, and a horizontal interval is increased when a perpendicular interval between the horizontal segment and a circuit component which is close to the horizontal segment is smaller than a predetermined threshold at S90.
The method will be specifically described with reference to the drawings. It is assumed that a result of the wiring in the S60 is set into a state shown in FIG. 20. In FIG. 24, the cell row is not shown for simplicity. FIG. 24 is the same as the drawings used for the explanation of the Patent Document 1 and the reference numerals have been described above. It is assumed that the net 50B is extracted as the wiring causing the violation of the design restriction in the S70. At the subsequent 580, as shown in FIG. 29, a width of the horizontal segment 50B is increased. At the S90, if a wiring spacing 42 between the first wiring layers does not satisfy a minimum interval rule specified by a design rule due to an increase in the wiring width at the S80, the wiring spacing 42 between the first layer wirings is increased so as to satisfy the design rule by a compaction in a perpendicular direction.    Patent Document 1: JP-A-5-63085 Publication    Patent Document 2: JP-A-2005-222214 Publication    Patent Document 3: Japanese Patent No. 3137072 Publication    Patent Document 4: JP-A-2001-34646 Publication
The methods (the Patent Documents 1 to 3) of generating a flattened pattern (or a flattened dummy) according to the prior art in the Patent Documents 1 to 3 do not take the wiring resistance to be the fourth drawback into consideration. Moreover, all of the flattened pattern generating methods according to the prior art serve to generate a redundant wiring which does not come in contact with a wiring in an empty region and only use the empty region for mainly generating a flattened pattern, and do not consider that a wiring resistance is reduced by using the empty region and there is a problem in that the wiring resistance is increased.
As in the semiconductor integrated circuit optimizing method described in the Patent Document 4, moreover, when the wiring width is simply increased after the wiring, a wiring spacing rule 42 depending on the wiring width (a design rule in which a wiring spacing is to be increased with an increase in a wiring width) is applied to a deep sub-micron process. For this reason, a design becomes complicated.
In a designing method based on a minimum wiring width and wiring spacing as in a wiring grid used in an automatic place and route tool in an ASIC designing technique, particularly, there is a problem in that a design is complicated if a wide wiring is partially handled.